1. Field of Invention
The present invention relates to an integrated circuit (IC) fabrication process. More particularly, the present invention relates to a method for checking the alignment accuracy in a photolithograph process for defining an upper layer with respective to a lower layer on a wafer.
2. Description of Related Art
Generally, besides having to control the critical dimension, alignment accuracy (AA) is also an important factor for determining the success of a photolithograph process of a wafer. Accordingly, the measurement of alignment accuracy, in other words, the measurement of overlay accuracy is an important issue in a semiconductor process. Further, the overlay mark is tool for measuring an overlay error, in which the alignment between a pattern of a photoresist layer and a previously formed layer on the wafer after the lithograph process, is determined.
FIG. 1 includes drawing (a) and drawing (b), wherein drawing (b) is a cross-sectional view of drawing (a) along the cutting line I-I. FIG. II also includes drawing (a) and drawing (b), wherein drawing (b) is a cross-sectional view of drawing (a) along the cutting line II-II. Referring to FIG. 1, when the lower layer 102 in the device region of a wafer is patterned, two trenches 122a and 122b in the Y-direction and two trenches 124a, 124b in the X-direction are concurrently formed in the non-device region as an outer mark. After the formation of a subsequent upper layer on the wafer, a photolithograph process is performed to concurrently form a photoresist pattern in the device region and two bar-shape photoresist patterns 132a and 132b along the Y direction and two bar-shape photoresist patterns 134a and 134b along the X direction in the non-device region as an inner mark of an overlay mark.
Conventionally, the method of using the overlay mark for measuring the alignment accuracy includes measuring the interior profiles and the exterior profiles, respectively, of the Y-directional trenches 122a and 122b to obtain the center lines S122a and S122b. Further, the center lines S132a and S132b of the Y-directional photoresist patterns 132a and 132b are obtained. Thereafter, the distance dy1 between the center lines S122a and S132a and the distance dy2 between the center lines S122b and S132b are calculated. If dy1 is equal to dy2, the overlay error in the y direction is 0. The same method is used to determine the overlay error in the X direction. If the overlay errors is both the X direction and the Y direction are not within the acceptable range of deviations, the photoresist layer is removed and the photolithograph process is repeated until the overlay errors are lower than the acceptable range of deviations.
However, during the fabrication of the trenches 122a, 122b, 124a, 124b as the overlay marks, the varying positions of the trenches or other factors in the fabrication process may induce unbalance stresses to the lower layer on the wafer. Ultimately, the profiles of two corresponding trenches become asymmetrical, resulting with the X-directional trenches 124a and 124b or the Y-directional trenches 122a and 122b tilted asymmetrically or their dimensions being different as shown in FIG. 2. In FIG. 2, the size of the Y-directional trench 122b′ is greater than the size of the Y-directional trench 122a′. If the conventional alignment accuracy method is applied for calculating the overlay error, the resulting center lines of the Y-directional trenches 122a′/122b′ are shifted to the positions respectively depicted as S122a′ and S122b′. Consequently, the differences between the distances dy1′ and dy2′, which are the distances between the center lines S122a′ and S122b′ of the trenches 122a/122b and the center lines S132a/S132b of the neighboring photoresist pattern, are not the actual overly error in the Y direction. Ultimately, an overlay shift is resulted. The overlay shift in the X direction and the overlay shift in the Y direction adversely affect the overlay accuracy. More particularly, even dy1 and dy2 are equal, the overlay error is not necessary 0. Similarly, even dx1 and dx2 are equal, the overlay error in the X-direction is not necessary 0. Hence, the conventional method is unreliable for determining alignment accuracy between the photoresist pattern and the wafer.